(a). Field of the Invention
The present invention relates to a small size semiconductor package and, more particularly, to a small size semiconductor package of a resin mold type used for a high frequency semiconductor device.
(b). Description of the Related Art
A GaAs FET is generally used for a high frequency electronic equipment such as a BS converter, a portable telephone or a radar system. A ceramic package is generally used for the GaAs FET, in order to reduce a power loss due to a parasitic capacitance or parasitic inductance especially in the high frequency range and to obtain desired characteristics. However, the ceramic package is extremely expensive to raise the total costs for the GaAs FET.
To reduce the manufacturing costs for a high frequency semiconductor device, a resin mold package is recently proposed instead of the ceramic package, for example, in JP-A-2(1990)-17664.
In the conventional semiconductor package for a high frequency bipolar transistor, a configuration has been generally employed in which an emitter lead is disposed between the collector lead and the base lead to thereby improve the transistor characteristics in the high frequency range.
FIG. 1 shows an equivalent circuit diagram for a high frequency bipolar transistor operating in the microwave range and received in a package, wherein parasitic capacitances C.sub.bco and C.sub.c2 exist between collector electrode (C) and base electrode (B). By arranging the emitter lead between the collector lead and base lead, these parasitic capacitances C.sub.bco and C.sub.c2 can be canceled to improve the transistor characteristics in the high frequency range.
FIG. 2 shows an example of a schematic top plan view of the semiconductor package of FIG. 1, which satisfies a SC-56 mini-mold transistor package design defined in Electric Industries Association of Japan (EIAJ) (hereinafter called SC-56 package). The SC-56 package comprises a collector lead 21 roughly occupying the central area and upper-right area of the package, a semiconductor element 14 mounted on the central area of the collector lead 21, a base lead 22 occupying the lower-left area, an emitter lead 23 occupying the upper-left area and the lower-right area and extending through the space between the collector lead 21 and base lead 22, and a plurality of bonding wires 15 for electrically connecting the pads of the semiconductor element 14 to the base lead 22 and emitter lead 23.
The SC-56 package is of a small external size as low as 2.9.times.1.5 mm, and exhibits excellent characteristics in the high frequency range. However, it has only a small heat capacity for the collector electrode, and accordingly, the application thereof is limited only to a transistor element of a small electric power, i.e., limited to a signal circuit.
FIG. 3A shows a schematic top plan view of another conventional package defined as SOT-89 package in EIAJ. The SOT-89 package has at the central area thereof a collector lead 21 having a large heat capacity and thus a function of heat dissipation, a transistor element 14 mounted on the central area of the emitter lead 21, a base lead 22 at the left area, and an emitter lead 23 at the right area, all of which are molded with a resin mold package. The SOT-89 package is of a large size as high as 4.5.times.2.5 mm and the leads used therein have a thickness of 0.4 mm. In this configuration, the emitter lead 23 cannot be disposed between the base lead 22 and collector lead 21 in order to improve the transistor characteristics in the high frequency range.
It may be considered to modify the SOT-89 package by disposing the emitter lead 23 between the base lead 22 and collector lead 21 to improve the transistor characteristics in the high frequency range. FIG. 3B shows the inferred arrangement modified from the SOT-89 package of FIG. 3A, wherein a gap of 0.4 mm or more is provided between each two of the inner leads due to the practical limit of the current etching or punching press technique, taking account of the 0.4-mm-thick leads which generally requires a gap of 0.4 mm or more between the leads. As understood from FIG. 3B, the emitter lead 23 disposed between the base lead 22 and collector lead 21 reduces the collector lead area to the extent that is not practical for mounting the transistor element 14 for heat dissipation.
Patent Publication JP-A-4(1992)-31326 proposes a technique for improving the lead density by reducing the gap between the leads down to below the thickness of the leads. The technique first uses a general etching or pressing technique for a lead frame having an extension portion formed in a tie bar of the lead frame, then uses lateral pressing at the extension portion to reduce the width of the tie bar to obtain a sufficient gap between the leads. This process, however, requires a special work process for the lead frame to thereby complicate the fabrication process for the package. In addition, it is difficult to reduce the width of the leads with a high accuracy because the side surface of the lead is not always vertical to the top surface thereof.